2D/2.5D Advanced Packaging for Interposers

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Design

Simulation

Production

Testing

Reliability Testing

Analysis

Chiplets & Heterogeneous Integration

A chiplet is a physically realized and tested (hardened) IP with a standard communication interface manufactured in a silicon wafer to reduce cost by increasing the manufacturing yield and reusability across applications.

The value proposition:

  • Flexibility in picking the best process node for the IP
  • Better yield due to small die size
  • Shorter IC design cycle and integration complexity by using pre-existing chiplets
  • High-performance 3D die stacking techniques for better integration with the chip system and power/performance integration
  • Accelerated speed
  • Lower development cost offered by modular integration
  • Lower manufacturing costs by purchasing known-good die (KGD)
  • Volume manufacturing cost advantage when the same chiplet(s) are used in many designs

Advanced Packaging production technology

  • Chips Micro-bumps (D-10um/P-10um)
  • WLCSP / Cu-pillar bond
  • Flip Chip / Die Bond
  • Silicon Interposer (TSV)
  • Chips C4-bumps (D-100um/P-100um)
  • BGA/CSP/FCBGA Solder Ball (D-200um/P-200um)
  • Chips Underfill
  • Liquid Molding
  • Auto Testing
  • Marking / Packaged

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